Super-micro-computer SUPER X7DB8 Manual de usuario descargar pdf (Pagina 15)

Chapter 1: Introduction

1-9

1-2 Chipset Overview

Built upon the functionality and the capability of the 5000P (Blackford) chipset, the

X7DB8/X7DBE motherboard provides the performance and feature set required

for dual processor-based servers with conﬁ guration options optimized for commu-

nications, presentation, storage, computation or database applications. The 5000P

(Blackford) chipset supports single or dual Xeon 64-bit dual core processor(s) with

front side bus speeds of up to 1.333 GHz. The chipset consists of the 5000P

(Blackford) Memory Controller Hub (MCH), the Enterprise South Bridge 2 (ESB2),

and the I/O subsystem (PXH).

The 5000P (Blackford) MCH chipset is designed for symmetric multiprocessing

across two independent front side bus interfaces. Each front side bus uses a 64-

bit wide, 1333 MHz data bus that transfers data at 10.7 GB/sec. In addition, the

5000P (Blackford) chipset offers a wide range of RAS features, including memory

interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory

mirroring and memory sparing.

The Xeon Dual Core Processor Features

Designed to be used with conjunction of the 5000P (Blackford) chipset, the Xeon

dual core Processor provides a feature set as follows:

The Xeon Dual Core Processors

*L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)

*L2 Cache Size: 4MB/2MB (per core)

*Data Bus Transfer Rate: 8.5 GB/s

*Package: FC-LGA6/FC-LGA4, 771 Lands

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 129 130

Sin comentarios

Super-micro-computer SUPER X7DB8 Manual de usuario Pagina 15